Trench in semiconductor device and formation method thereof

ABSTRACT

A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Also, etching is performed on the LOCOS oxide layer and the silicon wafer to a desired depth to form a trench. During this process, etching is performed such that the LOCOS oxide layer is left remaining on the silicon wafer at an area corresponding to edges of the trench. An insulation layer is deposited such that the trench is filled with a material of the insulation layer. The present invention also provides a trench in a semiconductor device used as a device isolation region formed in a silicon wafer. Upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.

This application is a divisional of U.S. application Ser. No.10/728,699, filed Dec. 5, 2003 (Attorney Docket No. OPP031052US),pending.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a trench in asemiconductor device and a formation method thereof.

(b) Description of the Related Art

A LOCOS (local oxidation of silicon) isolation structure, in which asemiconductor substrate is thermally oxidized using a nitride layer as amask, is widely used as an isolation structure for conventionalsemiconductor devices. However, the formation of a bird's beakconfiguration and an increase in a field region result from LOCOSisolation. As a result, there are limitations to how small the devicecan be made when using the LOCOS isolation structure.

In an effort to overcome these problems, STI (shallow trench isolation)is used in place of LOCOS isolation. In STI, a trench is formed in asemiconductor substrate, and an insulation material is filled in thetrench. Since the formation is limited to the size of the trench, whichhas as its object size a field region size, this configuration worksfavorably toward making the semiconductor device small.

U.S. Pat. Nos. 5,521,422, 5,956,598, 5,989,977, 6,001,706, and 6,495,430are conventional techniques related to STI.

A conventional method for forming a trench in a semiconductor devicewill be described with reference to FIGS. 1 a and 1 b.

With reference first to FIG. 1 a, a pad oxide layer 2 then a siliconnitride layer 3 are deposited on a semiconductor substrate 1. Next, aphotoresist layer is deposited on the silicon nitride layer 3, then thephotoresist layer is exposed to remove a portion thereof correspondingto where a trench is to be formed to thereby realize a photoresist layerpattern 4.

Subsequently, with reference to FIG. 1 b, using the photoresist layerpattern 4 as a mask, the exposed portion of the silicon nitride layer 3then the pad oxide layer 2 and a predetermined section of thesemiconductor substrate 1 (i.e., a section corresponding to apredetermined depth) under the removed section of the pad oxide layer 2are dry-etched. A trench 100 is therefore formed in the semiconductorsubstrate 1. The photoresist layer pattern 4 is removed after theformation of the trench 100, then a cleaning process is performed.

Next, a liner oxide layer 5 is formed over all exposed elements of thesilicon nitride layer 3, the pad oxide layer 2, and inner walls of thetrench 100, after which a trench oxide layer 6 is thickly deposited onthe liner oxide layer 5 at least until the trench 100 is completelyfilled.

The liner oxide layer 5 minimizes the stress transferred to the trenchregion during deposition of the trench oxide layer 6. The liner oxidelayer 5 also prevents the uneven formation of the trench oxide layer 6caused by differences in deposition rates on the semiconductor substrate1 and the silicon nitride layer 3, which results from the difference inthe materials of the semiconductor substrate 1 and the silicon nitridelayer 3. In addition, with the formation of the liner oxide layer 5,upper corner areas of the semiconductor substrate 1 adjacent to thetrench 100 are rounded (i.e., prevented from being sharply pointed)following a subsequent trench isolation process.

Next, chemical-mechanical polishing is performed on the trench oxidelayer 6 and the liner oxide layer 5 until the silicon nitride layer 3 isexposed, that is, until the trench oxide layer 6 and the liner oxidelayer 5 are flattened and flush with the silicon nitride layer 3. Thiscompletes the trench isolation process.

However, in the conventional STI as described above, it is difficult torealize the rounding of the upper corners of the semiconductor substratethat are adjacent to the trench through only the formation of the lineroxide layer. This becomes increasingly difficult as the degree ofintegration of the device is raised.

Accordingly, upper areas of the semiconductor substrate adjacent to thetrench are formed with sharp corners. If an electric charge isconcentrated in these corner areas, a dielectric breakdown voltage isreduced. There is therefore a need to realize a method for rounding theupper corner areas of the semiconductor substrate adjacent to thetrench.

SUMMARY OF THE INVENTION

In one exemplary embodiment of the present invention, there is provideda trench in a semiconductor device and a formation method thereof inwhich upper corner areas of a semiconductor device adjacent to thetrench are formed in a rounded configuration. The present invention alsoprovides an STI configuration that is advantageous in the formation of asmall device.

In an exemplary embodiment of the present invention, a method of forminga trench in a semiconductor device is provided. The method includesforming a sacrificial layer on a silicon wafer and selectively etchingthe sacrificial layer to form a LOCOS opening having a predeterminedwidth; performing thermal oxidation on a portion of the silicon waferexposed through the LOCOS opening to form a LOCOS oxide layer; etchingthe LOCOS oxide layer and the silicon wafer to a desired depth to form atrench, the etching being performed such that the LOCOS oxide layer isleft remaining on an area of the silicon wafer corresponding to edges ofthe trench; and forming an insulation layer such that the trench isfilled with a material of the insulation layer.

During formation of the LOCOS opening, a predetermined width of thesacrificial layer located at edges of a region where the trench is to beformed is etched, or the sacrificial layer is etched to a width greaterby a predetermined amount than a region to be occupied by a trench.

In etching a predetermined width of the sacrificial layer located atedges of a region where the trench is to be formed, the sacrificiallayer is etched to a width of 50-500 Å. Further, in etching thesacrificial layer to a width greater by a predetermined amount than aregion to be occupied by the trench, the sacrificial layer is etched toa width that is at most 400 Å greater than the trench.

During formation of the trench, a photoresist layer is deposited on theLOCOS oxide layer and the sacrificial layer, then the photoresist layeris exposed and developed to form a photoresist layer pattern thatexposes an area of the LOCOS oxide layer where the trench is to beformed, after which the photoresist layer pattern is used as a mask toetch the exposed area of the LOCOS oxide layer and the silicon wafer toa desired depth.

The photoresist layer pattern is formed so that at most 200 Å of a widthof the LOCOS oxide layer positioned at edges of the trench is coveredsuch that at most 400 Å of an entire cross-sectional width is covered,and the remainder of the LOCOS layer is exposed.

The method further includes forming a liner oxide layer prior to formingthe insulation layer, the liner oxide layer covering inner walls of thetrench and the remaining region of the LOCOS oxide layer. The lineroxide layer is formed to a thickness of 100-500 Å.

The method further includes removing the remaining region of the LOCOSoxide layer and forming a liner oxide layer prior to forming theinsulation layer.

The method further includes performing chemical-mechanical polishing onthe insulation layer following the formation of the same until thesacrificial layer is exposed.

The method further includes forming a pad oxide layer on the siliconwafer prior to forming the sacrificial layer, and forming thesacrificial layer on the pad oxide layer. The sacrificial layer is madeof a material that is polished more slowly than the insulation layerthat fills the trench. A nitride layer may be used as the sacrificiallayer, in which case the nitride layer is formed to a thickness of1500-3000 Å.

In another exemplary embodiment of the present invention, there isprovided a trench in a semiconductor device used as a device isolationregion formed in a silicon wafer. Upper corner areas of the siliconwafer adjacent to the trench are rounded, and a LOCOS oxide layer isformed on the corner areas.

A liner oxide layer is formed on inner walls of the trench and on theLOCOS oxide layer. The liner oxide layer is formed to a thickness of100-500 Å.

The LOCOS oxide layer is formed to a thickness of at most 200 Å.

Further, a liner oxide layer is formed along inner walls of the trenchand on the LOCOS oxide layer, to a thickness of 100-500 Å.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which together with the specification,illustrate exemplary embodiments of the present invention, and, togetherwith the description, serve to explain the principles of the presentinvention.

FIGS. 1 a and 1 b are sectional views used to describe a conventionalmethod for forming a trench in a semiconductor device.

FIGS. 2 a through 2 e are sectional views used to describe a method forforming a trench in a semiconductor device according to an exemplaryembodiment of the present invention.

FIGS. 3 a through 3 e are sectional views used to describe a method forforming a trench in a semiconductor device according to anotherexemplary embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will now be described indetail with reference to the accompanying drawings.

Referring to FIG. 2 e, a trench in a semiconductor device according toan exemplary embodiment of the present invention is formed as a deviceseparation region in a silicon wafer 11 and is filled with an insulationmaterial, preferably an oxide layer 18 (i.e., a trench oxide layer).

A LOCOS (local oxidation of silicon) oxide layer 15 is formed along bothedges of the trench such that upper corners of the silicon wafer 11adjacent to the trench are rounded. The LOCOS oxide layer 15 is formedto a width of 200 Å or less. Since the upper corners of the siliconwafer 11 are rounded even with the formation of a minimal amount of theLOCOS oxide layer 15, it is not possible to establish a lower limitvalue of the width of the LOCOS oxide layer 15.

A liner oxide layer 17 is formed along inner walls of the trench and onthe LOCOS oxide layer 15. The liner oxide layer 17 is formed to athickness of 100-500 Å.

A method for forming a trench in a semiconductor device according to anexemplary embodiment of the present invention will now be described withreference to FIGS. 2 a through 2 e.

With reference first to FIG. 2 a, a pad oxide layer 12 is thinlydeposited on a semiconductor substrate 11. Next, a nitride layer 13 isdeposited on the pad oxide layer 12, then a photoresist layer isdeposited on the nitride layer 13. The photoresist layer is exposed toremove a portion thereof corresponding to where a trench is to be formedto thereby realize a first photoresist layer pattern 14. The firstphotoresist layer pattern 14 exposes a width of the nitride layer 13that is slightly greater than a width of a region where the trench is tobe formed.

When forming the first photoresist layer pattern 14, an area that islarger than an area of where the trench is to be formed corresponds to asize of a LOCOS oxide layer to be formed in a subsequent process. Thisremoved area of the photoresist layer to realize the first photoresistlayer pattern 14 may be varied depending on the desired degree ofroundness of upper corners of the silicon wafer 11. Preferably, an areathat is larger than the area where the trench is to be formed is 200 Åor less on each side, and 400 Å or less of an overall cross-sectionalwidth.

The pad oxide layer 12 is selectively deposited to minimize stress ofthe nitride layer 13 from being transmitted to the silicon wafer 11.Preferably, the pad oxide layer 12 is deposited thinly at a thickness of100-300 Å, more preferably 200 Å.

The nitride layer 13 has a polish speed that is less than that of amaterial of an oxide layer used to fill the trench, to thereby act as apolish stop layer during chemical-mechanical polishing of the trenchoxide layer. The nitride layer 13 is preferably deposited to a thicknessof 1500-3000 Å. As an example, the nitride layer 13 may be formed to athickness of 2000 Å.

Next, with reference to FIG. 2 b, the first photoresist layer pattern 14is used as a mask to etch the exposed area of the nitride layer 13 andthe pad oxide layer 12 thereunder to thereby form a LOCOS opening 100that exposes the silicon wafer 11. The first photoresist layer pattern14 is removed following this procedure, then a cleaning process isperformed.

Next, thermal oxidation of the silicon wafer 11 is performed through theLOCOS opening 100 to form a LOCOS oxide layer 15 in this area of theexposed silicon wafer 11. The LOCOS oxide layer 15 is formed into theshape of an ellipse as a result of thermal oxidation characteristics ofthe silicon wafer 11. Further, by varying a thickness of the LOCOS oxidelayer 15, the degree of roundness of an upper portion of the trench,which will be formed in a subsequent process, may be controlled.

Referring now to FIG. 2 c, a photoresist layer is deposited on the LOCOSoxide layer 15 and the nitride layer 13, then the photoresist layer isexposed and developed to form a second photoresist layer pattern 16 withan opening that exposes an area corresponding to where the trench is tobe formed. The opening of the second photoresist layer pattern 16 istypically positioned above an approximately center position of the LOCOSoxide layer 15, and an area of the second photoresist layer pattern 16defining its opening covers 200 Å or less of the LOCOS oxide layer 15.That is, if a cross section of the structure as shown in FIG. 2 c isdescribed, the photoresist layer pattern 16 is formed such that 200 Å orless of opposing sides of the LOCOS oxide layer 15 is covered by thephotoresist layer pattern 16, and the remainder of the LOCOS oxide layer15 is exposed.

Subsequently, with reference to FIG. 2 d, using the second photoresistlayer pattern 16 as a mask, an exposed portion of the LOCOS oxide layer15 is etched. The silicon wafer 11 is then etched in the same area to apredetermined depth. This results in the formation of a trench 200 suchthat a portion of the LOCOS oxide layer 15 is left remaining on portionsof the silicon wafer 11 at edges of the trench 200. This remainingportion of the LOCOS oxide layer 15 acts to round the upper corners ofthe silicon wafer 11 adjacent to the trench 200.

Next, with reference to FIG. 2 e, a trench oxide layer 18 is thicklydeposited on all exposed elements of inner walls of the trench 200, theLOCOS oxide layer 15, and the nitride layer 13 until the trench 200 issufficiently filled. Prior to depositing the trench oxide layer 18, aliner oxide layer 17 may be formed to a thickness of 100-500 Å over allexposed elements of the inner walls of the trench 200, the LOCOS oxidelayer 15, and the nitride layer 13. The liner oxide layer 17 improvesdeposition characteristics of the trench oxide layer 18. Further, priorto depositing the trench oxide layer 18, the liner oxide layer 17 may beformed to a thickness of 100-500 Å after removing the remaining portionof the LOCOS oxide layer 15.

Following the above processes, chemical-mechanical polishing isperformed on the trench oxide layer 18 to flatten the same, then thenitride layer 13 and the pad oxide layer 12 are removed by a wet etchingprocess. This completes the shallow trench isolation process.

FIGS. 3 a through 3 e are sectional views used to describe a method forforming a trench in a semiconductor device according to anotherexemplary embodiment of the present invention.

Referring first to FIG. 3 a, a pad oxide layer 12 is thinly formed on asilicon wafer 11, then a nitride layer 13 is deposited on the pad oxidelayer 12. Next, a photoresist layer is deposited on the nitride layer13, then the photoresist layer is exposed such that areas of apredetermined width of the photoresist layer positioned at edges of aregion where a trench is to be formed are removed to thereby form afirst photoresist layer pattern 14.

During formation of the photoresist layer pattern 14, a width W of thephotoresist layer positioned at edges of the region where a trench is tobe formed corresponds to a size of a LOCOS oxide layer to be formed in asubsequent process. The width W may be varied depending on the desireddegree of rounding of upper corners of the silicon wafer 11 adjacent toa trench. Preferably, the width W is 50-500 Å.

Referring to FIG. 3 b, using the first photoresist layer pattern 14 as amask, exposed areas of the nitride layer 13 then the pad oxide layer 12thereunder are etched to form LOCOS openings 100. The first photoresistlayer pattern 14 is removed following the formation of the LOCOSopenings 100, then a cleaning process is performed.

Subsequently, thermal oxidation is performed on areas of the siliconwafer 11 exposed through the LOCOS holes 100 such that LOCOS oxidelayers 15 are formed therein. The LOCOS oxide layers 15 are formed intothe shape of an ellipse as a result of thermal oxidation characteristicsof the silicon wafer 11. Further, by varying a thickness of the LOCOSoxide layers 15, the degree of roundness of upper corners of a trench tobe formed in a subsequent process may be controlled.

Next, referring to FIG. 3 c, a photoresist layer is deposited on theLOCOS oxide layers 15 and the nitride layer 13, then the photoresistlayer is exposed and developed to form a second photoresist layerpattern 16 with an opening that exposes an area corresponding to where atrench is to be formed. The opening of the second photoresist layerpattern 16 is typically positioned above approximately a center positionof the LOCOS oxide layer 15. Also, an area of the second photoresistlayer pattern 16 defining its opening covers 200 Å or less of the LOCOSoxide layer 15, and the opening exposes the remainder of the LOCOS oxidelayer 15.

Subsequently, with reference to FIG. 3 d, using the second photoresistlayer pattern 16 as a mask, exposed portions of the LOCOS oxide layers15, the nitride layer 13, and the pad oxide layer 12 are etched. Thesilicon wafer 11 is then etched in the same area to a predetermineddepth. This results in the formation of a trench 200 such that a portionof the LOCOS oxide layer 15 is left remaining on portions of the siliconwafer 11 at edges of the trench 200. This remaining portion of the LOCOSoxide layer 15 acts to round the upper corners of the silicon wafer 11adjacent to the trench 200.

Next, with reference to FIG. 3 e, a trench oxide layer 18 is thicklydeposited on all exposed elements of inner walls of the trench 200, theLOCOS oxide layer 15, and the nitride layer 13 until the trench 200 issufficiently filled. Prior to depositing the trench oxide layer 18, aliner oxide layer 17 may be formed to a thickness of 100-500 Å over allexposed elements of the inner walls of the trench 200, the LOCOS oxidelayer 15, and the nitride layer 13. The liner oxide layer 17 improvesdeposition characteristics of the trench oxide layer 18. Further, priorto depositing the trench oxide layer 18, the liner oxide layer 17 may beformed to a thickness of 100-500 Å after removing the remaining portionof the LOCOS oxide layer 15.

Following the above processes, chemical-mechanical polishing isperformed on the trench oxide layer 18 to flatten the same, then thenitride layer 13 and the pad oxide layer 12 are removed by a wet etchingprocess. This completes the shallow trench isolation process.

As described above, a LOCOS oxide layer is formed to a small width atpredetermined locations corresponding to edge portions of a trenchbefore formation of the same. As a result, upper corners of the siliconwafer adjacent to the trench are formed into a rounded configuration.This allows the device to be made to small sizes, which provedproblematic with conventional methods in which corner portions of thesilicon wafer adjacent to the trench become sharply pointed withincreases in the degree of integration of the device.

Although embodiments of the present invention have been described indetail hereinabove in connection with certain exemplary embodiments, itshould be understood that the invention is not limited to the disclosedexemplary embodiments, but, on the contrary is intended to cover variousmodifications and/or equivalent arrangements included within the spiritand scope of the present invention, as defined in the appended claims.

1. A trench in a semiconductor device used as a device isolation regionformed in a silicon wafer, in which upper corner areas of the siliconwafer adjacent to the trench are rounded, and a LOCOS oxide layer isformed on the corner areas.
 2. The trench of claim 1, wherein a lineroxide layer is formed on inner walls of the trench and on the LOCOSoxide layer.
 3. The trench of claim 2, wherein the liner oxide layer isformed to a thickness of 100-500 Å.
 4. The trench of claim 1, whereinthe LOCOS oxide layer is formed to a thickness of at most 200 Å.
 5. Thetrench of claim 4, wherein a liner oxide layer is formed along innerwalls of the trench and on the LOCOS oxide layer, to a thickness of100-500 Å.
 6. A device isolation region in a silicon wafer, comprising:a trench in the silicon wafer, rounded upper corner areas of the siliconwafer adjacent to the trench, and a LOCOS oxide layer on the roundedupper corner areas.
 7. The device isolation region of claim 6, furthercomprising a liner oxide layer on inner walls of the trench and on theLOCOS oxide layer.
 8. The device isolation region of claim 7, whereinthe liner oxide layer has a thickness of 100-500 Å.
 9. The deviceisolation region of claim 6, wherein the LOCOS oxide layer has athickness of at most 200 Å.
 10. The device isolation region of claim 9,further comprising a liner oxide layer along inner walls of the trenchand on the LOCOS oxide layer, having a thickness of 100-500 Å.
 11. Thedevice isolation region of claim 6, wherein the LOCOS oxide layer on therounded upper corner areas has a width of at most 200 Å.
 12. The deviceisolation region of claim 6, further comprising an insulation layer inthe trench.
 13. The device isolation region of claim 7, furthercomprising an insulation layer on the liner oxide layer in the trench.14. A device isolation region, comprising: trench in a silicon wafer;rounded upper corner areas of the silicon wafer adjacent to the trench;and a liner oxide layer on inner walls of the trench and on the roundedupper corner areas; and an insulation layer filling the trench.
 15. Thedevice isolation region of claim 14, further comprising.
 16. The deviceisolation region of claim 14, wherein the liner oxide layer has athickness of 100-500 Å.
 17. The device isolation region of claim 14,wherein the rounded upper corner areas have a width of at most 200 Å.18. A semiconductor device, comprising the device isolation region ofclaim 14.